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DSP-based designs

Baseband decoder

          

 The boards shown here have been designed for the leading US satellite radio service provider XM Satellite Radio. ZP designed custom hardware for testing and validation requirements of their baseband decoder, initially using a RAM version of the custom DSP, and later employing a masked version of their processor (see upper left).

Both RAM and masked version were designed to plug on the Aptix Reconfigurable Prototyping System that was used during the debug phase of the custom hardware section.

DSP boards for algorithm development

  

The system above is a complete development platform based on the RAM version of a custom DSP; a high-speed IEEE-1284 based host interface is available on-board. Along with custom, kernel-mode drivers, a download transfer rate of up to 150 KB/s is ensured. Stereo analog (24-bit) and digital (SPDIF) inputs and outputs are present. An Altera Flex10K FPGA connects the various on-board peripherals to the DSP. Testing of the system has been done with a dedicated Tcl-based command shell, allowing the DSP developer the possibility of rapidly testing the interaction with DSP algorithms.

 

A version with reduced features has been designed for the same customer in minimal time, supporting the validation phase of the algorithms.

DSP+ARM boards for VoIP 

    

Various custom development platforms have been developed following the specifications from customers. These dual-processor platforms are targeted for telecom applications.

The system on the left is being used for embedded firmware development in the telecom field.
The boards hosts an ARM7 TDMI CPU with a local Ethernet controller, a D950 DSP with external memories; a high-density Xilinx Virtex FPGA offers up to 600,000 gates for interfacing external devices.
The system has been completely designed and tested in-house.

The system on the right is a powerful new platform for firmware development, sporting an ARM7TDMI section with local memory banks and Ethernet interface, an ST-100 based data processing section, two 800,000 gates Xilinx Virtex FPGAs.
The system has been designed, fabricated, assembled and tested in-house.